1. Field of the Invention
The present invention relates to a bus control device at least provided with an internal bus and an internal unit, and an information processing system using the bus control device. In particular, the present invention relates to a bus control device that mediates between a CPU and a local memory to control the use of an internal bus by the CPU and an internal unit, and an information processing system using the bus control device.
2. Description of the Related Art
A conventional bus control device will be described with reference to FIG. 13. FIG. 13 shows an exemplary configuration of a conventional bus control device. As shown in FIG. 13, a bus control device 91 includes an internal bus 96, an external interface 92, a memory interface 94, and a plurality of internal units 93. The external interface 92, the memory interface 94, and a plurality of internal units 93 are connected to the internal bus 96.
The memory interface 94 is provided with a bus arbiter 95 for arbitrating in the use of the internal bus 96. The external interface 92 is connected to an external CPU (central processing unit) 100 via a system bus 101. The memory interface 94 is connected directly to an external local memory 102.
In the case where the CPU 100 accesses the local memory 102, the CPU 100 first accesses the external interface 92. When accessed from the CPU 100, the external interface 92 requests the use of the internal bus 96 with respect to the bus arbiter 95. In the case where none of a plurality of internal units 93 uses the internal bus 96, the bus arbiter 95 permits the external interface 92 to use the internal bus 96.
When the external interface 92 is permitted to use the internal bus 96, the external interface 92 transfers data with respect to the local memory 102 via the memory interface 94 on the internal bus 96 side, and the external interface 92 transfers data with respect to the CPU 100 on the system bus 101 side.
In FIG. 13, reference numeral 97a denotes a bus request signal for the internal unit 93 to request the use of the internal bus 96 with respect to the bus arbiter 95, and reference numeral 97b denotes a bus request signal for the external interface 92 to request the use of the internal bus 96 with respect to the bus arbiter 95. Reference numeral 98a denotes a bus permission signal for the bus arbiter 95 to permit the internal unit 93 to use the internal bus 96. Reference numeral 98b denotes a bus permission signal for the bus arbiter 95 to permit the external interface 92 to use the internal bus 96.
Assume that the external interface 92 requests the use of the internal bus 96 with respect to the bus arbiter 95, and either one of the internal units 93 has been using the internal bus 96 continuously for a long period of time, and transferring data with respect to the local memory 102 via the memory interface 94.
In this case, the bus arbiter 95 cannot permit the CPU 100 to use the internal bus 96. Therefore, the external interface 92 outputs a stand-by signal to the CPU 100. When, the stand-by signal is output, the CPU 100 is put in a stand-by state, and continues to wait for a response from the external interface 92. Furthermore, the CPU 100 in a stand-by state cannot access another device connected via the system bus 101. Therefore, when the stand-by period of the CPU 100 is prolonged, the performance of the entire system may be degraded.
In order to solve the above-mentioned problem, a system is proposed in which a plurality of shared memories shared by a plurality of devices are provided (e.g., see JP 63(1988)-181068 A). If such a system is used, a plurality of devices can write/read data simultaneously. This can suppress degradation of the performance of the entire due to a prolonged stand-by period.
However, in the above-mentioned system, a plurality of shared memories are required for constituting one system, which increases a cost.